Knowledge-Driven AI for SystemVerilog Assertions: A Verification Framework of Methodologies, Processes, and Coding Rules

This book represents a paradigm shift in how we approach assertion-based verification. Rather than viewing AI as a replacement for human expertise, we demonstrate how expert knowledge can guide and constrain AI to produce industrial-grade SystemVerilog assertions that meet the rigorous demands of formal verification and simulation. Central to this approach is a structured dialogue in which the AI actively interrogates requirements before writing a single line of code — surfacing ambiguities in timing boundaries, signal directionality, and logical contradictions that human engineers often leave implicit. By treating requirement clarification as a first-class step, not an afterthought, the methodology ensures that every assertion traces directly to an unambiguous, formally stated intent. The result is a collaborative workflow where human expertise defines the boundaries of what is correct, and AI operates precisely within those boundaries — catching the category of errors that are most costly when discovered late in a design cycle.

Links to downloadable AI RAG rules for SVA are provided

http://systemverilog.us/About_Cohen_Chibani_Book.pdf